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29F0408
32 Megabit (4M x 8-Bit) Flash Memory
Logic Diagram
Memory
FEATURES:
* Single 5.0 V supply * Excellent Single Event Effect * - SELTH: > 60 MeV/mg/cm2 * - SEUTH: = 37 MeV/mg/cm2 - SEU saturated cross section: 2E-6 cm2/bit * Organization: - Memory cell array: (4M + 128k) bit x 8bit - Data register: (512 + 16) bit x 8bit * Automatic program and erase - Page program: (512 + 16) Byte - Block erase: (8K + 256) Byte - Status register * 528-Byte page read operation - Random access: 10 s (max) - Serial page access: 50 ns (min) * Fast write cycle time - Program time: 250 s (typ) - Block erase time: 2 ms (typ) * Command/address/data multiplexed I/O port * Hardware data protection - Program/erase lockout during power transitions * Reliable CMOS floating-gate technology - Endurance: 1,000,000 program/erase cycles - Data retention: 10 years * Command register operation * 44 pin flat package
DESCRIPTION:
Maxwell Technologies' 29F0408 high-performance flash memory. The 29F0408 is a 4M (4,194,304) x 8-bit NAND Flash Memory with a spare 128K (131,072) x 8-bit. A program operation programs the 528-byte page in 250 s and an erase operation can be performed in 2 ms on an 8K-byte block. Data within a page can be read out at 50 ns cycle time per byte. The on-chip write controller automates all program and erase functions, including pulse repetition, where required, and internal verify and margining of data. Even write-intensive systems can take advantage of the 29F0408's extended reliability of 1,000,000 program/erase cycles by providing either ECC (Error Correction Code) or real time mapping-out algorithm. These algorithms have been implemented in many mass storage applications. The spare 16 bytes of a page combined with the other 512 bytes can be utilized by system-level ECC. The 29F0408 is an optimum solution for large non-volatile storage applications such as solid state storage, digital voice recorder, digital still camera and other portable applications requiring nonvolatility. Maxwell Technologies' patented RAD-PAK(R) packaging technology incorporates radiation shielding in the microcircuit package. Capable of surviving in space environments, the 29F0408 is ideal for satellite, spacecraft, and space probe missions. It is available with packaging and screening up to Class S.
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32 Megabit (4M x 8-Bit) Flash Memory
29F0408
TABLE 1. PINOUT DESCRIPTION
PIN 2 SYMBOL Command Latch Enable (CLE) DESCRIPTION The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
3
Address Latch Enable The ALE input controls the path activation for address and input data to the internal (ALE) address/data register. Addresses are latched on the rising edge or WE with ALE high, and input data is latched when ALE is low. Chip Enable (CE) The CE input is the device selection control. When CE goes high during a read operation, the device is returned to standby mode. However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to standby mode. The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. The RE inputs is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. The SE input controls the spare area selection when SE is high, the device is deselected the spare area during Read1, Sequential data input and page Program.
43
4 42
Write Enable (WE) Read Enable (RE)
40 18-21, 24-27 5 41
Spare Area Enable (SE)
I/O Port: I/O0 ~ I/O7 The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to High-Z when the chip is deselected or when the outputs are disabled. Write Protect (WP) Read/Busy (R/B) The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low. The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to High-Z condition when the chip is deselected or when outputs are disabled. Not Connected Ground Supply Voltage Output Buffer Voltage
6-17, 28-39 1, 22 44 23
NC VSS VCC VCCQ
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32 Megabit (4M x 8-Bit) Flash Memory
TABLE 2. 29F0408 ABSOLUTE MAXIMUM RATINGS 1,2
PARAMETER Voltage on any pin relative to VSS Operating Temperature Storage temperature Short circuit output current SYMBOL VIN TBIAS TSTG IOS MIN -0.6 -40 -65 --
29F0408
MAX 7.0 125 150 5 UNIT V
C C
mA
1. Minimum DC voltage is -0.3 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods < 30 ns. Maximum DC voltage on input/output pins is VCC + 0.3 V which, during transitions, may overshoot to VCC + 2.0 V for periods < 20 ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect reliability.
TABLE 3. 29F0408 RECOMMENDED OPERATING CONDITIONS
(VOLTAGE REFERENCE TO GND, TA = -40 TO 125 C) PARAMETER Supply voltage Supply voltage Input High Voltage Input Low Voltage SYMBOL VCC VSS VIH VIL MIN 4.5 0 2.4 -0.3 TYP 5.0 0 --MAX 5.5 0 VCC 0.5 0.8 UNIT V V V V
TABLE 4. DELTA LIMITS
PARAMTER ICC1 ISB1 ISB2 CONDITION 10% 10% 10%
TABLE 5. 29F0408 AC TEST CONDITION
(VCC = 5 V 10%, TA = -40 TO 125 C, UNLESS OTHERWISE NOTED) PARAMETER Input pulse levels Input rise times Input and output timing levels MIN 0.4 -0.8 MAX 2.6 5.0 2.0 UNIT V ns V
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32 Megabit (4M x 8-Bit) Flash Memory
TABLE 6. 29F0408 DC AND OPERATING CHARACTERISTICS
(VCC = 5 V 10%, TA = -40 TO 125 C, UNLESS OTHERWISE NOTED) PARAMETER Operating current Sequential read Program Erase Stand-by-current (TTL) Stand-by current (CMOS) Input leakage current Output leakage current Input high voltage, all inputs Input low voltage, all inputs Output high voltage level Output low voltage level Outuput low current (R/B) SYMBOL ICC1 ICC2 ICC3 ISB1 ISB2 ILI ILO VIH VIL VOH VOL IOL (R/B) IOH = -400 A IOL = 2.1 mA VOL = 0.4 V CE = VIH, WP = SE = 0V/VCC CE = VCC - 0.2, WP = SE = 0V/VCC VIN = 0 to 5.5 V VOUT = 0 to 5.5 V TEST CONDITIONS tCYCLE = 50 ns CE = VIL, IOUT = 0 mA SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 MIN ------10 -10 2.0 -2.4 -8 TYP 15 15 25 -10 ------10
29F0408
MAX 30 30 40 1 100 10 10 -0.8 -0.4 --
UNIT mA
mA uA uA uA V V V V mA
TABLE 7. 29F0408 CAPACITANCE 1
PARAMETER Input/Output capacitance Input capacitance 1. Capacitance Guarenteed by design. SYMBOL CI/O CIN TEST CONDITION VIL = 0V VIN = 0V MIN --MAX 10 10 UNIT pF pF
TABLE 8. 29F0408 MODE SELECTION
CLE H L H L L ALE L H L H L CE L L L L L WE RE H H H H H SE X X X X L/H 1 WP X X H H H Data Input Write Mode Read Mode MODE Command Input Address Input (3 Clock) Command Input Address Input (3 Clock)
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TABLE 8. 29F0408 MODE SELECTION
CLE L L X X X X ALE L L X X X2 X CE L L X X X H WE H H X X X X H X X X X RE SE L/H
1
29F0408
WP X X H H L MODE Sequential Read & Data Output During Read (Busy) During Program (Busy) During Erase (Busy) Write Protect Stand-by
L/H 1 L/H X X 0V/VCC3
1
0V/VCC3
1. When SE is high, spare area is deselected. 2. X can be VIL or VIH. 3. WP should be biased to CMOS high or CMOS low for standby.
TABLE 9. 29F0408 PROGRAM/ERASE CHARACTERISTICS
(VCC = 5 V 10%, TA =-40 TO +125C, UNLESS OTHERWISE NOTED) PARAMETER Program time Number of partial program cycles in the same page Block erase time SYMBOL tPROG NOP tBERS MIN ---TYP 0.25 -2 MAX 1.5 10 10 UNIT ms cycles ms
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32 Megabit (4M x 8-Bit) Flash Memory
29F0408
TABLE 10. 29F0408 AC TIMING CHARACTERISTICS FOR COMMAND/ADDRESS/DATA INPUT
(VCC = 5 V 10%, TA =-40 TO +125 C, UNLESS OTHERWISE NOTED) PARAMETER CLE set-up time CLE hold time CE setup time CE hold time WE pulse width ALE setup time ALE hold time Data setup time Data hold time Write cycle time WE high hold time SYMBOL tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 MIN 0 10 0 10 25 0 10 20 10 50 15 MAX -----------UNIT ns ns ns ns ns ns ns ns ns ns ns
TABLE 11. 29F0408 AC CHARACTERISTICS FOR OPERATION
(VCC = 5 V 10%, TA = -40 TO +125 C, UNLESS OTHERWISE NOTED) PARAMETER Data transfer from cell to register ALE to RE delay (read ID) ALE to RE delay (read cycle) CE to RE delay (ID read) Ready to RE low1 RE pulse width WE high to busy Read cycle time RE access time RE high to output Hi-Z CE high to output Hi-Z RE high hold time Output Hi-Z to RE low Last RE high to busy (at sequential read) CE high to ready (in case of interception by CE at read) 2 CE high hold time (at the last serial read) 4 RE low to status output SYMBOL tR tAR1 tAR2 tCR tRR tRP tWR tRC tREA tRHZ tCHZ tREH tIR tRB tCRY tCEH tRSTO
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SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
MIN -150 50 100 20 30 -50 -15 -15 0 --100 --
MAX 10 -----100 -35 30 20 --100 50 + tr (R/B)
3
UNIT s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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32 Megabit (4M x 8-Bit) Flash Memory
TABLE 11. 29F0408 AC CHARACTERISTICS FOR OPERATION
(VCC = 5 V 10%, TA = -40 TO +125 C, UNLESS OTHERWISE NOTED) PARAMETER CE low to status output RE high to WE low WE high to RE low RE access time (read ID) Device resetting time (read/program/erase/after erase suspend) 1. Not Tested SYMBOL tCSTO RHWY tWHR tREADID tRST SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 MIN -0 60 ---
29F0408
MAX 45 --35 5/10/500
UNIT ns ns ns ns s
2. If CE goes high within 30 ns after the rising edge of the last RE, R/B will not return to VOL. 3. The time to Ready depends on the value of the pull-up resistor tied to R/B pin. 4. To break the sequential read cycle, CE must be held high for longer than tCEH.
TABLE 12. 29F0408 VALID BLOCK 1,2
PARAMETER Valid Block Number SYMBOL NVB MIN 502 TYP 508 MAX 512 UNIT Blocks
1. The device may include valid blocks. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these invalid blocks for program and erase. During its lifetime of 10 years and/or 1 million program/erase cycles, the minimum number of valid blocks are guaranteed though its initial number could be reduced. (Refer to following technical note) 2. The 1st block, which is placed on the 00h block address, is guaranteed to be a valid block.
NAND FLASH TECHNICAL NOTES
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by the manufacturer. Typically, an invalid block will contain a single bad bit. The information regarding the invalid block(s) is called as the invalid block information. The invalid block information is written to the 1st or the 2nd page of the invalid block(s) with 00h data. Devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the invalid block(s) via address mapping. The 1st block of the NAND Flash, however, is fully guaranteed to be a valid block.
Identifying Invalid Block(s)
All device locations are erased (FFh) except locations where the invalid block information is written prior to shipping. Since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original invalid
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29F0408
block information and create the invalid block table via the following suggested flow chart (Figure 1). Any intentional erasure of the original block information is prohibited.
FIGURE 1. FLOW CHART TO CREATE INVALID BLOCK TABLE
Error in write or read operation
Over its lifetime, the additional invalid blocks may occur. Through the tight process control and intensive testing, additional block failure rate is minimized which is projected below 0.1% until 1 million program/erase cycles. Refer to the qualification report for the actual data. The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.
FAILURE MODE Write Erase failure Program failure
DETECTION AND COUNTERMEASURE Status read after erase AE Block replacement Status read after program AE Block replacement Read back (verify after program) AE Block replacement or ECC correction Verify ECC AE ECC correction
Read
Single bit failure
ECC: Error Correcting Code AE Hamming Code, etc. Example. 1-bit correction and 2-bit detection
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FIGURE 2. PROGRAM FLOW CHART
29F0408
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29F0408
FIGURE 3. ERASE FLOW CHART
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29F0408
FIGURE 4. READ FLOW CHART
FIGURE 5. BLOCK REPLACEMENT
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Pointer Operation:
29F0408
The 29F0408 has three modes to set the destination of the pointer. The pointer is set to "A" area by the "00h" command, to "B" area by the "01h" command, and to "C" area by the "50h" command. The Destination Pointer Table shows the destination of the pointer, and the block diagram shows the diagram of its operation.
TABLE 12. DESTINATION OF POINTER TABLE
FIGURE 6. BLOCK DIAGRAM OF POINTER OPERATION
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32 Megabit (4M x 8-Bit) Flash Memory
29F0408
FIGURE 7. EXAMPLES OF PROGRAMMING WITH SUCCESSIVE POINTER OPERATION
TABLE 13. POINT STATUS AFTER EACH OPERATION
System Interface Using CE don't-care. For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption.
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32 Megabit (4M x 8-Bit) Flash Memory
29F0408
FIGURE 8. PROGRAM OPERATION WITH CE DON'T CARE
Timing requirements: If CE is is exerted high during data-loading, tCS must be minimum 10ns and tWC must be increased accordingly.
Timing requirements: If CE is is exerted high during sequentialdata-reading, the falling edge of CE to valid data(tCEA) must be kept greater than 45ns.
FIGURE 9. READ OPERATION WITH CE DON'T CARE
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32 Megabit (4M x 8-Bit) Flash Memory
FIGURE 10. COMMAND LATCH CYCLE
29F0408
FIGURE 11. ADDRESS LATCH CYCLE
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FIGURE 12. INPUT DATA LATCH CYCLE
29F0408
FIGURE 13. SEQUENTIAL OUT CYCLE AFTER READ (CLE = L, WE = H, ALE = L)
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29F0408
FIGURE 14. STATUS READ CYCLE
FIGURE 15. READ1 OPERATION (READ ONE PAGE)
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FIGURE 16. READ1 OPERATION (INTERCEPTED BY CE)
29F0408
FIGURE 17. READ2 OPERATION (READ ONE PAGE)
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29F0408
FIGURE 18. SEQUENTIAL ROW READ OPERATION
FIGURE 19. PAGE PROGRAM OPERATION
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32 Megabit (4M x 8-Bit) Flash Memory
FIGURE 20. BLOCK ERASE OPERATION (ERASE ONE BLOCK)
29F0408
FIGURE 21. MANUFACTURE & DEVICE ID READ OPERATION
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DEVICE OPERATION PAGE READ
29F0408
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with three address cycles. Once the command is latched, it does not need to be written for the following page read operation. Three types of operations are available : random read, serial page read and sequential read. The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred to the data registers in less than 10 ms(tR). The CPU can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50 ns cycle time by sequentially pulsing RE with CE staying low. High to low transitions of the RE clock output the data starting from the selected column address up to the last column address(column 511 or 527 depending on state of SE pin). After the data of last column address is clocked out, the next page is automatically selected for sequential read. Waiting 10 s again allows for reading of the selected page. The sequential read operation is terminated by bringing CE high. The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to 527 may be selectively accessed by writing the Read2 command with SE pin low. Toggling SE during operation is prohibited. Addresses A0 to A3 set the starting address of the spare area while addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 command (00h/01h) is needed to move the pointer back to the main area. Figures 22 thru 25 show typical sequence and timings for each read operation.
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32 Megabit (4M x 8-Bit) Flash Memory
29F0408
FIGURE 22. READ1 OPERATION
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32 Megabit (4M x 8-Bit) Flash Memory
29F0408
FIGURE 23. READ2 OPERATION
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32 Megabit (4M x 8-Bit) Flash Memory
29F0408
FIGURE 24. SEQUENTIAL ROW READ1 OPERATION
FIGURE 25. SEQUENTIAL READ2 OPERATION (SE = FIXED LOW)
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PAGE PROGRAM
29F0408
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed ten. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register, followed by a nonvolatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can be started from 2nd half array. About the pointer operation, please refer to the attached technical notes.The serial data loading period begins by inputting the Serial Data Input command (80H), followed by the three cycle address input and then serial data loading. The bytes other than those to be programmed do not need to be loaded. The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without perviously entering the serial data will not initiate the programming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The CPU can detect the completion of a program cycle by monitoring the R/B output, or the Status bit (I/O6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit (I/O0) may be checked (Figure 26). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.
FIGURE 26. PROGRAM & READ STATUS OPERATION
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32 Megabit (4M x 8-Bit) Flash Memory
BLOCK ERASE
29F0408
The Erase operation can erase on a block (8K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command (60h). Only address A13 to A21 is valid while A9 to A12 is ignored. The addresses of the block to be erased to FFh. The Erase Confirm command (D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit (I/O0) may be checked. Figure 27 details the sequence.
FIGURE 27. BLOCK ERASE OPERATION
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is complete, and whether the program or erase operation completed successfully. After writing 70h command to the command register, a read cycle outputs the contents of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 14 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command (00h or 50h) should be given before sequential page read cycle.
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32 Megabit (4M x 8-Bit) Flash Memory
29F0408
TABLE 14. READ STATUS REGISTER DEFINITION
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Two read cycles sequentially output the manufacture code(ECh), and the device code (E3h) respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 28 shows the operation sequence.
FIGURE 28. READ ID OPERATION
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RESET
29F0408
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase modes, the reset operation will abort these operation. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. Internal address registers are cleared to "0"s and data registers to "1"s. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to table 15 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted to by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 29 below.
FIGURE 29. RESET OPERATION
TABLE 15. DEVICE STATUS
DATA PROTECTION
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever VCC is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down as shown in Figure 30. The two step command sequence for program/erase provides additional software protection.
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32 Megabit (4M x 8-Bit) Flash Memory
29F0408
FIGURE 30. AC WAVEFORMS FOR POWER TRANSITION
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is begin after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. An appropriate pull-up resister is required for proper operation and the value may be calculated by following equation.
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29F0408
FIGURE 31. READY/BUSY
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29F0408
44 PIN RAD-PAK(R) FLAT PACKAGE
SYMBOL MIN A b c D E E1 E2 E3 e L Q S1 N 0.350 0.022 0.005 0.132 0.015 0.006 1.188 0.668 -0.450 0.098 DIMENSION NOM 0.147 0.017 0.008 1.200 0.675 -0.455 0.110 0.050 BSC 0.370 0.027 -44 0.398 0.032 -MAX 0.160 0.019 0.10 1.212 0.682 0.705 0.460 0.122
Note: All dimensions in inches
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32 Megabit (4M x 8-Bit) Flash Memory
Important Notice:
29F0408
These data sheets are created using the chip manufacturer's published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies' products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies' liability shall be limited to replacement of defective parts.
11.08.02 Rev 2
All data sheets are subject to change without notice
32
(c)2002 Maxwell Technologies All rights reserved.
32 Megabit (4M x 8-Bit) Flash Memory
Product Ordering Options
Model Number 29F0408 RP F X Feature
29F0408
Option Details
Screening Flow
Monolithic S = Maxwell Class S B = Maxwell Class B I = Industrial (testing @ -40C, +25C, +125C) E = Engineering (testing @ +25C)
Package
F = Flat Pack
Radiation Feature
RP = RAD-PAK(R) package
Base Product Nomenclature
32 Megabit (4M x 8-Bit) Flash Memory
11.08.02 Rev 2
All data sheets are subject to change without notice
33
(c)2002 Maxwell Technologies All rights reserved.

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